Method of Forming a Fully Silicided Semiconductor Device with Independent Gate and Source/Drain Doping and Related Device

ABSTRACT

A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

BACKGROUND

In today's electronics industry, devices are continually gettingsmaller, faster, and using less power, while simultaneously being ableto support and perform a greater number of increasingly complex andsophisticated functions. One reason for these trends is an everincreasing demand for small, portable and multifunctional electronicdevices. For example, cellular phones, personal computing devices, andpersonal audio devices (e.g., MP3 players) are in great demand in theconsumer market. Such electronic devices rely on a limited power source(e.g., batteries) while providing ever-increasing processingcapabilities and storage capacity.

Accordingly, there is a continuing trend in the semiconductor industryto manufacture low-cost, high-performance, and low-power integratedcircuits (ICs). These goals have been achieved in great part by scalingdown the dimensions of semiconductor ICs and thus increasing device andcircuit densities. Achieving higher densities calls for smaller featuresizes, smaller separations between features and layers, and more precisefeature shapes. The scaling down of IC dimensions can facilitate fastercircuit performance (e.g., faster switching speeds) and can lead tohigher effective yield in IC fabrication processes by providing (i.e.,“packing”) more circuits on a semiconductor die and/or more die on asemiconductor wafer.

A fundamental building block of semiconductor ICs is the metal-oxidesemiconductor (MOS) transistor. FIG. 1 illustrates a cross-section of abasic MOS transistor 100. The transistor 100 is fabricated on asemiconductor substrate 110 and comprises a gate stack 120. The gatestack 120 comprises a gate dielectric 130 (e.g., silicon dioxide) and agate electrode 140 (e.g., polysilicon) on the gate dielectric 130. Thetransistor 100 also comprises a source region 150 and a drain region 160each formed within the semiconductor substrate 110. A channel 170 isdefined between the source and drain regions 150, 160, under the gatedielectric 130, and within the semiconductor substrate 110. The channel170 has an associated channel length “L” and an associated channel width“W”. When a bias voltage greater than a threshold voltage (Vt) (i.e.,turn-on voltage) for the transistor 100 is applied to the gate electrode140 along with a concurrently applied bias voltage between the sourceand drain regions 150, 160, an electric current (e.g., a transistordrive current) flows between the source and drain regions 150, 160through the channel 170. The amount of drive current developed for agiven bias voltage (e.g., applied to the gate electrode 140 or betweenthe source and drain regions 150, 160) is a function of, among others,the width-to-length ratio (W/L) of the channel 170.

MOS transistors have become cheaper, faster, and less power-hungry witheach new technology generation as the physical dimensions and appliedvoltages have been scaled down. To date, most transistor scaling hasbeen achieved by thinning the gate dielectric 130 or reducing thechannel length “L”. However, as transistor scaling moves into thenanometer-scale regime, scaling the gate dielectric 130 thickness or thechannel length “L” is not sufficient as new phenomenon appear (e.g.,leakage current flowing through the gate dielectric 130, polysilicongate electrode depletion effects (“poly-depletion”), and contactresistance effects), which reduce the transistor drive current. Thepoly-depletion effect is characterized by a polysilicon gate electrode140 that is no longer fully conductive and contributes an additionalcapacitance (in series) between the gate electrode 140 and the siliconsubstrate 110, resulting in reduced transistor drive current. New gatedielectrics having a high dielectric constant (“high-K” gatedielectrics) have been introduced in an effort to improve transistordrive current without increasing the leakage current through the gatedielectric 130. However, high-K gate dielectrics face reliability andcompatibility issues with polysilicon gate electrodes such as poor workfunction control, which results in, for example, transistors having anunsuitable threshold voltage (Vt). For other gate dielectric materialssuch as silicon dioxide, polysilicon gate electrodes become problematicwith scaling due to the poly-depletion effect and contact resistanceproblems.

SUMMARY

The problems noted above are solved in large part by a method of forminga fully silicided semiconductor device with independent gate andsource/drain doping and related device. At least some of theillustrative embodiments are methods comprising forming a gate stackover a substrate (the gate stack comprising a polysilicon layer and ablocking layer), and performing an ion implantation into an activeregion of the substrate adjacent to the gate stack (the blocking layersubstantially blocks the ion implantation from the polysilicon layer).

Other illustrative embodiments are semiconductor devices comprising asubstrate, a first gate stack on the substrate (the first gate stackhaving a first height, and the first gate stack comprising a blockinglayer substantially impervious to ion implantation), and a spacer alonga sidewall of the first gate stack (the spacer having a second height).The first height is substantially equal to the second height.

Yet other illustrative embodiments are semiconductor devices comprisinga substrate, a gate stack on the substrate (the gate stack having afirst height, and the gate stack comprising a silicide layer), and aspacer along a sidewall of the gate stack (the spacer having a secondheight). The first height is substantially unequal to the second height.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more detailed description of the various embodiments, referencewill now be made to the accompanying drawings, wherein:

FIG. 1 shows a perspective view of a MOS transistor;

FIG. 2 shows a cross sectional view illustrating the formation of a MOStransistor after formation of a polysilicon layer;

FIG. 3 shows a cross sectional view illustrating the formation of a MOStransistor after formation of a blocking layer;

FIG. 4 shows a cross sectional view illustrating the formation of a MOStransistor after formation of a gate stack and source/drain extensionregions;

FIG. 5 shows a cross sectional view illustrating the formation of a MOStransistor after formation of source and drain regions;

FIG. 6 shows a cross sectional view illustrating the formation of a MOStransistor after formation of a cover layer;

FIG. 7 shows a cross sectional view illustrating the formation of a MOStransistor after a chemical mechanical polishing (CMP) process;

FIG. 8 shows a cross sectional view illustrating the formation of a MOStransistor after removal of the blocking layer;

FIG. 9 shows a cross sectional view illustrating the formation of a MOStransistor after formation of a metal layer as a precursor tosilicidation of the polysilicon layer;

FIG. 10 shows a cross sectional view illustrating the formation of a MOStransistor after silicidation of the polysilicon layer;

FIG. 11 shows a cross sectional view illustrating the formation of a MOStransistor after removal of the cover layer;

FIG. 12 shows a cross sectional view illustrating the formation of a MOStransistor after formation of a metal layer as a precursor tosilicidation of the source and drain regions; and

FIG. 13 shows a cross sectional view illustrating the formation of a MOStransistor after silicidation of the source and drain regions.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claimsto refer to particular system components. As one skilled in the art willappreciate, various companies may refer to a component by differentnames. This document does not intend to distinguish between componentsthat differ in name but not function. In the following discussion and inthe claims, the terms “including” and “comprising” are used in anopen-ended fashion, and thus should be interpreted to mean “including,but not limited to . . . ”. Also, the term “couple” or “couples” isintended to mean either an indirect or direct connection. Thus, if afirst device couples to a second device, that connection may be througha direct connection, or through an indirect connection via other devicesand connections.

A “blocking” layer means a layer that substantially blocks, for example,a dopant species delivered by way of ion implantation. Also, the term“active region” means a region wherein a semiconductor device is formedwithin and/or on a semiconductor substrate, and wherein the activeregion does not comprise isolation structures, such as shallow trenchisolation (STI) structures or field oxide (FOX) regions.

Unless otherwise stated, when a layer is said to be “deposited over thesubstrate” or “formed over the substrate”, it means that the layer isdeposited or formed over any topography that already exists on thesubstrate.

The term “thermal budget” is used to define an amount of thermal energytransferred to a semiconductor wafer (e.g., during a high-temperatureprocess) and is given as a product of temperature (e.g., in degreesKelvin) and time (e.g., in seconds). Low thermal budget processes arepreferred, for example, to prevent dopant redistribution orelectromigration.

DETAILED DESCRIPTION

The following discussion is directed to various embodiments of theinvention. Although one or more of these embodiments may be preferred,the embodiments disclosed should not be interpreted, or otherwise used,as limiting the scope of the disclosure, including the claims, unlessotherwise specified. In addition, one skilled in the art will understandthat the following description has broad application, and the discussionof any embodiment is meant only to be exemplary of that embodiment, andnot intended to intimate that the scope of the disclosure, including theclaims, is limited to that embodiment. Also, layers and/or elementsdepicted herein are illustrated with particular dimensions and/ororientations relative to one another for purposes of simplicity and easeof understanding, and actual dimensions and/or orientations of thelayers and/or elements may differ substantially from that illustratedherein.

The subject matter disclosed herein is directed to methods associatedwith construction of a semiconductor device, such as a metal-oxidesemiconductor (MOS) transistor. A semiconductor is a material (e.g.,silicon or germanium) having properties somewhere between a conductorand an insulator. By adding impurities (e.g., by a process known as“doping”), a semiconductor can be classified as being electron-rich(N-type, wherein “N” stands for Negative) or electron-poor (P-type,wherein “P” stands for Positive). Through a series of semiconductorprocessing techniques (e.g., deposition, photolithography, etching, ionimplantation), semiconductor materials are used to make semiconductordevices (e.g., transistors) which are in turn used to make integratedcircuits (ICs). Moreover, N-type MOS transistors (NMOS) and P-type MOS(PMOS) transistors are often used together to form complementarymetal-oxide semiconductor (CMOS) ICs.

Metallic gate electrodes in semiconductor CMOS ICs overcomeelectrostatic and transport issues (e.g., poly-depletion, thresholdvoltage control, and contact resistance) associated with polysilicongate electrodes. In particular, embodiments disclosed herein relate tointegrating a metallic gate electrode into a CMOS process flow by way ofa fully silicided (FUSI) process flow. Silicidation of a polysilicongate electrode involves depositing a layer of metal (e.g., Nickel) overthe polysilicon gate and performing an anneal to induce a reactionbetween the metal and the polysilicon gate. During the anneal, adeposited layer of metal may diffuse into the polysilicon gate and reactto form a metal silicide (e.g., nickel silicide). In a FUSI processflow, the deposited layer of metal diffuses into, and reacts with, theentire polysilicon gate to form a “fully” silicided metal gate, asopposed to diffusing into, and reacting with, less than the entirepolysilicon gate to form a partially silicided metal gate, wherein anunreacted polysilicon layer remains within the gate electrode. In otherFUSI process flows, silicon from the polysilicon gate diffuses into thedeposited metal layer as opposed to the metal diffusing into thepolysilicon gate; however, the result is the same in that a fullysilicided metal gate is formed. In some embodiments, a layer of metal isreacted with the source and drain regions of a transistor to form fullysilicided source and drain regions, which lessens the contact resistanceof the source and drain regions. Prior to the FUSI flow, the polysilicongate electrode and the source and drain regions are simultaneously dopedwith a dopant species (e.g., boron for PMOS transistors, and phosphorousor arsenic for NMOS transistors) using a self-aligned ion implantationprocess. To optimize the work function of the gate electrode during FUSIprocessing, it is desirable to separate, and independently control, thedoping of the gate electrode from the doping of the source and drainregions. Thus, the embodiments described herein provide a method ofintegrating a FUSI process flow into a CMOS flow while also providingindependent control of the doping of the gate electrode and the sourceand drain regions.

Referring to FIG. 2, isolation structures 205 are formed within asubstrate 200 in order to define an active area 232 and to electricallyisolate neighboring devices (e.g., transistors) from one another. Insome embodiments, the substrate 200 comprises, for example, a P-typesingle crystal silicon substrate that may be formed, for example, byepitaxial growth. In other embodiments, the substrate 200 comprises forexample, a silicon germanium (SiGe) substrate or a silicon-on-insulator(SOI) substrate. The isolation structures 205 can be formed, forexample, by a shallow trench isolation (STI) process. A well 210 is thenformed within the substrate 200, for example, by performing an ionimplantation into the substrate 200 followed by a high-temperatureanneal. The well 210 is doped with N-type dopants (e.g., phosphorous orarsenic) or P-type dopants (e.g., boron) depending on the type oftransistor (NMOS or PMOS) to be formed within the well 210. A dielectriclayer 225 is then formed over the substrate 200. The dielectric layer225 comprises a non-conductive material (e.g., a silicon oxide (i.e.,SiO₂), a silicon oxynitride, or a high dielectric constant (“high-K”)material such as a hafnium-based metal-oxide or a hafnium-basedsilicate). Depending on the material used for the dielectric layer 225,the dielectric layer 225 can be formed by a variety of techniques (e.g.,thermal oxidation, thermal oxidation followed by a thermal nitridation,atomic layer deposition (ALD), or chemical vapor deposition (CVD)). Apolysilicon layer 230 is then formed over the dielectric layer 225. Thepolysilicon layer 230 is formed, for example, by using a low-pressurechemical vapor deposition (LPCVD) process. During a FUSI process flow(discussed below), the polysilicon layer 230 is reacted with a metallayer to form a fully silicided metal gate electrode (e.g., a nickelsilicide gate electrode).

After formation of the polysilicon layer 230, an ion implantation 235 isoptionally performed for the purpose of doping the polysilicon layer230. Depending on the type of transistor being formed (NMOS or PMOS),the ion implantation 235 implants either N-type or P-type dopants.During the FUSI process flow, the fully silicided gate electrode retainsthe doping introduced during the ion implantation 235 such that theresulting fully silicided gate electrode has a work function andthreshold voltage (Vt) determined, at least in part, by the ionimplantation 235. In some embodiments, the dopant species of the ionimplantation 235 is selected in order to tune the work function of thegate electrode.

Referring to FIG. 3, after the ion implantation 235, a blocking layer240 is formed over the polysilicon layer 230. The blocking layer 240comprises a nitride layer (e.g., an LPCVD nitride layer or a plasmaenhanced chemical vapor deposition (PECVD) nitride layer). In someembodiments, the blocking layer 240 has a thickness of about 200Angstroms. In the embodiments described herein, the blocking layer 240blocks subsequent ion implantations (e.g., ion implantations used toform lightly-doped source/drain regions, or to form source/drainregions) from the polysilicon layer 230, and thus allows for theseparate and independent doping of the gate electrode (which is formedfrom the polysilicon layer 230) and the source/drain regions of thetransistor. In some embodiments, an antireflective coating (ARC) layer245 (e.g., an organic or inorganic ARC layer) is formed over theblocking layer 240 for patterning of a gate stack as discussed below.ARC layers are used to suppress reflections from underlying layersduring a lithographic process and to improve the quality of asubsequently patterned layer. The ARC layer 245 can be removed after thegate stack has been patterned and formed by an etching process. In someembodiments, the ARC layer 245 is not removed and is used to assist theblocking layer 240 with blocking of subsequent ion implantations. Inother embodiments, the blocking layer 240 comprises an ARC layer, and anadditional ARC layer (e.g., the ARC layer 245) is not formed over theblocking layer 240.

As shown in FIG. 4, the ARC layer 245 has been removed (e.g., by a wetor dry etching process), and the dielectric layer 225, the polysiliconlayer 230, and the blocking layer 240 (FIG. 3) have been patterned andetched to form a gate stack 250, wherein the gate stack 250 comprises adielectric layer 225A, a polysilicon layer 230A, and a blocking layer240A. The patterning process can be performed in any suitable manner,such as with lithographic techniques where lithography broadly refers toprocesses for transferring one or more patterns between various media.In photolithography, a light sensitive layer (e.g., photoresist) isformed upon a layer (e.g., by spin-coating) to which a pattern is to betransferred. The light sensitive layer is then patterned by exposing itto one or more types of radiation or light which selectively passthrough an intervening mask which comprises a pattern defined by varioustransparent and opaque regions. The light causes exposed or unexposedregions of the light sensitive layer to become more or less soluble,depending on the type of light sensitive layer used. A developer (i.e.,an etchant) is then used to remove the more soluble areas, therebytransferring the mask pattern to the light sensitive layer. Thepatterned light sensitive layer can then serve as a mask for anunderlying layer or layers, wherein the underlying layer or layers canbe etched to form the pattern as defined by the light sensitive layer.In particular, the dielectric layer 225, the polysilicon layer 230, andthe blocking layer 240 (FIG. 3) are patterned simultaneously by way ofthe light sensitive layer, and various (dry or wet) etchants can be usedto remove each of the layers in sequence, using the patterned lightsensitive layer as a mask. After etching of the dielectric layer 225,the polysilicon layer 230, and the blocking layer 240 (FIG. 3) to formthe gate stack 250, the light sensitive layer is stripped by an “ashing”process, wherein for example, the light sensitive layer is removed byexposure to an oxygen ambient at a high-temperature in the presence ofradio frequency (RF) power.

After forming the gate stack 250 and stripping the light sensitivelayer, an ion implantation 255 is performed. In particular, the ionimplantation 255 is performed into an active region 252 and into anactive region 262 in order to define a lightly doped source region 260and a lightly doped drain region 265. The gate stack 250 is alsosimultaneously subjected to the ion implantation 255; however, the gatestack 250 masks the substrate 200 from the ion implantation 255, suchthat the lightly doped source and drain regions 260, 265 are formedwithin the substrate 200 immediately adjacent to the gate stack 250.Moreover, the blocking layer 240A blocks the ion implantation 255 fromthe polysilicon layer 230A such that the doping of the polysilicon layer230A (i.e., the gate electrode) remains separate and independent of thedoping of the lightly doped source and drain regions 260, 265. In someembodiments, a thin conformal oxide or nitride layer may be depositedover the gate stack 250 prior to the ion implantation 255 in order toprotect sidewalls of the gate stack 250. Moreover, the thin conformaloxide or nitride layer can be used to protect sidewalls of thepolysilicon layer 230A. In some embodiments, the lightly doped sourceand drain regions 260, 265 may be equivalently referred to as source anddrain extension regions. A channel 275 is defined between the lightlydoped source region 260 and the lightly doped drain region 265, underthe gate dielectric 225A, and within the substrate 200. The channel 275has an associated channel length “L” and an associated channel width“W”. In some embodiments, a thermal process, such as a rapid thermalanneal, is performed to activate the dopants within the lightly dopedsource and drain regions 260, 265, which may cause a slight lateraldiffusion of the lightly doped source and drain regions 260, 265 underthe gate stack 250.

Referring now to FIG. 5, a spacer 270 is then formed on each sidewall ofthe gate stack 250. Each spacer 270 comprises an insulating materialsuch as an oxide and/or nitride based material. In some embodiments, thespacers 270 comprise a bistertiary-butylaminosilane (BTBAS) siliconnitride layer. The spacers 270 are formed by depositing one or morelayers of such material(s) over the substrate 200 in a conformal manner,followed by an anisotropic etch thereof, thereby removing spacermaterial from the top of the gate stack 250 and the substrate 200, whileleaving the spacers 270 on each of the sidewalls of the gate stack 250.Thereafter, an ion implantation 280 is performed. In particular, the ionimplantation 280 is performed into the exposed portion of the activeregion 252 and into the exposed portion of the active region 262 inorder to define a source region 285 and a drain region 290. The gatestack 250 and spacers 270 are also simultaneously subjected to the ionimplantation 280; however, the gate stack 250 and spacers 270 mask thesubstrate 200 from the ion implantation 280, such that the source anddrain regions 285, 290 are formed within the substrate 200 immediatelyadjacent to the spacers 270. Moreover, the blocking layer 240A blocksthe ion implantation 280 from the polysilicon layer 230A such that thedoping of the polysilicon layer 230A (i.e., the gate electrode) remainsseparate and independent of the doping of the source and drain regions285, 290. In addition, the spacers 270 serve to protect the sidewalls ofthe gate stack 250. In particular, the spacers 270 protect the sidewallsof the polysilicon layer 230A. In some embodiments, a thermal process,such as a rapid thermal anneal, is performed to activate the dopantswithin the source and drain regions 285, 290, which may cause a slightlateral diffusion of the source and drain regions 285, 290 under thespacers 270.

As shown in FIG. 6, once the source and drain regions 285, 290 have beenformed, a cover layer 295 is formed over the substrate 200 in aconformal manner. In some embodiments, the cover layer 295 comprises anitride layer such as a BTBAS silicon nitride layer and has a thicknessof about 50-100 Angstroms. An oxide layer 300 is then formed over thecover layer 295. The oxide layer 300 may comprise, for example, a layerof tetraethyl orthosilicate (TEOS), wherein the oxide layer 300 is used,at least in part, to form a planarized layer over the substrate 200. Insome embodiments, the oxide layer 300 has a thickness of about 2000Angstroms. In particular, the planarization of the oxide layer 300 isperformed by way of a chemical mechanical polishing (CMP) process,whereby the oxide layer 300 is mechanically polished by a polishing padwhile a chemical slurry containing abrasives chemically reacts with theoxide layer 300 to increase the removal rate of the oxide layer 300.Planarization by way of a CMP process is used, for example, to bring anentire topography within a depth of field (DOF) of a givenphotolithography system.

As shown in FIG. 7, the oxide layer 300 is polished (e.g., by way of aCMP process), until the cover layer 295 is exposed over the gate stack250. In some embodiments, the cover layer 295 may also be exposed overthe spacers 270. The cover layer 295 serves as a landing pad for the CMPprocess (i.e., as a CMP stopping layer) and as protection for the sourceand drain regions 285, 290 during silicidation of the polysilicon layer230A (discussed below). The exposed cover layer 295 and the blockinglayer 240A are then removed, as shown in FIG. 8. For example, in someembodiments, removal is accomplished by a dry etch comprising a reactiveion etch (RIE) (for removal of the cover layer 295) and a wet etchcomprising a hot phosphoric acid (for removal of the blocking layer240A). An acid (e.g., hydrofluoric acid (HF)) is then used to etch(i.e., to clean) the top of the exposed polysilicon layer 230A so thatthe subsequently formed silicide layer will be of a high quality. Duringthe acid etch or clean of the exposed polysilicon layer 230A, a portionof the oxide layer 300 may be removed. However, the cover layer 295 isnot effectively etched by the illustrative HF, and thus the cover layer295 remains as protection for the source and drain regions 285, 290during subsequent silicidation of the polysilicon layer 230A.

In FIG. 9, a metal layer 305 (e.g., nickel) is formed over the substrate200 as a precursor to silicidation of the polysilicon layer 230A. Insome embodiments, the metal layer 305 is formed by a physical method,such as evaporation or sputtering. After formation of the metal layer305, an anneal is performed to induce a reaction between the metal layer305 and the polysilicon layer 230A. As shown in FIG. 10, the reactionbetween the metal layer 305 and the polysilicon layer 230A creates asilicide layer 310 (e.g., a nickel silicide (NiSi) layer) which is nowthe transistor gate electrode. In particular, metal from the metal layer305 reacts with the entire polysilicon layer 230A to form a fullysilicided metal gate. Unreacted metal is then removed, for example, byway of a wet chemical etch. The source and drain regions 285, 290 remainprotected from the silicidation process by the cover layer 295. Inaddition, the thermal budget used to induce the reaction between themetal layer 305 and the polysilicon layer 230A is low as compared to,for example, the thermal budget used for activation of the source anddrain regions 285, 290. Therefore, the FUSI process can be performedafter higher thermal budget processing is complete. In some embodiments,after the silicide layer 310 is formed, another anneal may be performedin order to change the phase of the silicide layer 310 into alow-resistance phase. In yet other embodiments, the thermal budget usedto induce the reaction between the metal layer 305 and the polysiliconlayer 230A can be varied in order to form a silicide layer 310 havingone of a plurality of phases, wherein the phase of the silicide layerdetermines, at least in part, the work function of the silicide layer310. FIG. 10 also illustrates that there is a net volume expansion ofthe polysilicon layer 230A (FIG. 9) upon silicidation; however, in someembodiments, there remains a distance Δ between the top of the silicidelayer 310 and the top of the spacers 270. The distance Δ may beobserved, for example, by way of a cross-section transmission electronmicroscope (TEM) image of the device.

After formation of the silicide layer 310, any of the remaining oxidelayer 300 can be removed (e.g., with an HF etch), and the cover layer295 is removed (e.g., by way of a dry etch) resulting in a cross-sectionas shown in FIG. 11. FIG. 12 illustrates that a metal layer 315 (e.g.,nickel) is formed over the substrate 200 in order to perform asilicidation of the source and drain regions 285, 290. The metal layer315 may be formed by a physical method, and an anneal performed toinduce a reaction between the metal layer 315 and the source and drainregions 285, 290. As shown in FIG. 13, silicided source and drainregions 285A, 290A, which comprise, for example, nickel silicide (NiSi)regions are then formed. Unreacted metal is then removed. Since the gateelectrode (i.e., silicide layer 310) has already been fully silicided,silicidation of the source and drain regions does not affect thesilicide layer 310. Thereafter, other CMOS processing may follow (e.g.,interlayer dielectric and metallization layers can be formed).

The above discussion is meant to be illustrative of the principles andvarious embodiments of the present invention. Numerous variations andmodifications will become apparent to those skilled in the art once theabove disclosure is fully appreciated. For example, unless otherwiseindicated, any one or more of the layers set forth herein can be formedin any number of suitable ways (e.g., with spin-on techniques,sputtering techniques (e.g., magnetron and/or ion beam sputtering),thermal growth techniques, deposition techniques such as chemical vapordeposition (CVD), physical vapor deposition (PVD) and/or plasma enhancedchemical vapor deposition (PECVD), or atomic layer deposition (ALD)).Also, unless otherwise indicated, any one or more of the layers can bepatterned in any suitable manner (e.g., via lithographic and/or etchingtechniques). It is intended that the following claims be interpreted toembrace all such variations and modifications.

1-16. (canceled)
 17. A semiconductor device comprising: a substrate; agate stack on the substrate, the gate stack having a first height, andthe gate stack comprising a blocking layer substantially impervious toion implantation; and a spacer along a sidewall of the gate stack, thespacer having a second height; wherein the first height is substantiallyequal to the second height.
 18. The semiconductor device according toclaim 17 further comprising a cover layer on an active region of thesubstrate adjacent to the gate stack, wherein the cover layer protectsthe active region from silicidation.
 19. A semiconductor devicecomprising: a substrate; a gate stack on the substrate, the gate stackhaving a first height, and the gate stack comprising a silicide layer;and a spacer along a sidewall of the gate stack, the spacer having asecond height; wherein the first height is substantially unequal to thesecond height.
 20. The semiconductor device according to claim 19further comprising a silicided active region within the substrate. 16.The method according to claim 1 wherein forming the gate stack furthercomprises forming an antireflective layer over the blocking layer.
 17. Asemiconductor device comprising: a substrate; a gate stack on thesubstrate, the gate stack having a first height, and the gate stackcomprising a blocking layer substantially impervious to ionimplantation; and a spacer along a sidewall of the gate stack, thespacer having a second height; wherein the first height is substantiallyequal to the second height.
 18. The semiconductor device according toclaim 17 further comprising a cover layer on an active region of thesubstrate adjacent to the gate stack, wherein the cover layer protectsthe active region from silicidation.
 19. A semiconductor devicecomprising: a substrate; a gate stack on the substrate, the gate stackhaving a first height, and the gate stack comprising a silicide layer;and a spacer along a sidewall of the gate stack, the spacer having asecond height; wherein the first height is substantially unequal to thesecond height.
 20. The semiconductor device according to claim 19further comprising a silicided active region within the substrate.